Yuuki Araga

Publication Activity (10 Years)

Years Active: 2010-2021
Publications (10 Years): 8

Top Topics

Buffer Overflow

Protection Schemes

Top Venues

IEICE Electron. Express

Publications

Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Analysis and evaluation of noise coupling between through-silicon-vias. IEICE Electron. Express 18 (11) (2021)
Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Landside capacitor efficacy among multi-chip-module using Si-interposer. IEICE Electron. Express 18 (9) (2021)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55 (10) (2020)
Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC (2019)
Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi
Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs. 3DIC (2019)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC (2019)
Yuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne
A study on substrate noise coupling among TSVs in 3D chip stack. IEICE Electron. Express 15 (13) (2018)
Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi
Guard-ring monitoring system for inspecting defects in TSV-based data buses. 3DIC (2015)
Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi
Substrate monitoring system for inspecting defects in TSV-based data buses. 3DIC (2014)
Yuuki Araga, Nao Ueda, Yasumasa Takagi, Makoto Nagata
Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Akitaka Murata, Shuji Agatsuma, Daisaku Ikoma, Kouji Ichikawa, Takahiro Tsuda, Makoto Nagata, Kumpei Yoshikawa, Yuuki Araga, Yuji Harada
Noise analysis using on-chip waveform monitor in bandgap voltage references. EMC Compo (2013)
Takushi Hashida, Yuuki Araga, Makoto Nagata
A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength. IEICE Trans. Electron. (6) (2011)
Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne
In-tier diagnosis of power domains in 3D TSV ICs. 3DIC (2011)
Takushi Hashida, Yuuki Araga, Makoto Nagata
A diagnosis testbench of analog IP cores against on-chip environmental disturbances. VTS (2011)
Yuuki Araga, Takushi Hashida, Makoto Nagata
An on-chip waveform capturing technique pursuing minimum cost of integration. ISCAS (2010)