Naoya Watanabe

Publication Activity (10 Years)

Years Active: 1986-2021
Publications (10 Years): 11

Top Topics

Malicious Nodes

Integrated Circuit

Top Venues

Microelectron. Reliab.

IEICE Electron. Express

IEEE J. Solid State Circuits

Publications

Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Analysis and evaluation of noise coupling between through-silicon-vias. IEICE Electron. Express 18 (11) (2021)
Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Landside capacitor efficacy among multi-chip-module using Si-interposer. IEICE Electron. Express 18 (9) (2021)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55 (10) (2020)
Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC (2019)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC (2019)
Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. 3DIC (2019)
Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 79 (2017)
Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
Validation of TSV thermo-mechanical simulation by stress measurement. Microelectron. Reliab. 59 (2016)
Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura
Wet cleaning process for high-yield via-last TSV formation. 3DIC (2016)
Wei Feng, Bui Thanh Tung, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
Fabrication and stress analysis of annular-trench-isolated TSV. Microelectron. Reliab. 63 (2016)
Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 67 (2016)
Bui Thanh Tung, Naoya Watanabe, Masahiro Aoyagi, Katsuya Kikuchi
Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner. 3DIC (2015)
Bui Thanh Tung, Xiaojin Cheng, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, Masahiro Aoyagi
Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. 3DIC (2014)
Naoya Watanabe, Masahiro Aoyagi, Daisuke Katagawa, Tsubasa Bandoh, Takahiko Mitsui, Eiichi Yamamoto
Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal. 3DIC (2014)
Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
Analysis of thermal stress distribution for TSV with novel structure. 3DIC (2014)
Koji Nii, Teruhiko Amano, Naoya Watanabe, Minoru Yamawaki, Kenji Yoshinaga, Mihoko Wada, Isamu Hayashi
13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM. ISSCC (2014)
Masahiro Aoyagi, Naoya Watanabe, Motohiro Suzuki, Katsuya Kikuchi, Shunsuke Nemoto, Noriaki Arima, Misaki Ishizuka, Koji Suzuki, Toshio Shiomi
New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. 3DIC (2013)
Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. IEEE J. Solid State Circuits 48 (11) (2013)
Katsuya Kikuchi, Chihiro Ueda, Fumiaki Fujii, Yutaka Akiyama, Naoya Watanabe, Yasuhiro Kitamura, Toshio Gomyo, Toshikazu Okubo, Tetsuya Koyama, Tadashi Kamada, Masahiro Aoyagi, Kanji Otsuka
PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. 3DIC (2011)
Akihiro Ikeda, Naoya Watanabe, Tanemasa Asano
High frequency signal transmission characteristics of cone bump interconnections. 3DIC (2011)
Naoya Watanabe, Takumi Miyazaki, Masahiro Aoyagi, Kazuhiro Yoshikawa
Damage evaluation of wet-chemical silicon-wafer thinning process. 3DIC (2011)
Takanori Shuto, Naoya Watanabe, Akihiro Ikeda, Tanemasa Asano
Low-temperature bonding of LSI chips to PEN film using Au cone bump for heterogeneous integration. 3DIC (2011)
Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. (10) (2005)
Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34 (4) (1999)
Katsumi Dosaka, Akira Yamazaki, Naoya Watanabe, Hideaki Abe, Jun Ohtani, Toshiyuki Ogawa, Kazunori Ishihara, Masaki Kumanoya
A 90-MHz 16-Mb system integrated memory with direct interface to CPU. IEEE J. Solid State Circuits 31 (4) (1996)
Jaime Jungok Bae, Tatsuya Suda, Naoya Watanabe
Evaluation of the Effects of Protocol Processing Overhead in Error Recovery Schemes for a High-Speed Packet Switched Network: Link-by-Link versus Edge-to-Edge Schemes. IEEE J. Sel. Areas Commun. 9 (9) (1991)
Tatsuya Suda, Naoya Watanabe
Evaluation of error recovery schemes for a high-speed packet switched network: link-by-link versus edge-to-edge schemes. INFOCOM (1988)
Naoya Watanabe, Ken-ichi Yukimatsu, Toshiaki Doi, Masachika Ishizura, Etsugo Yoneda, Makoto Kawashima, Kazuhiro Hayashi
Network Testing for Digital Data Networks. ICC (1986)
Ken-ichi Yukimatsu, Naoya Watanabe, Takashi Honda
Multicast Communication Facilities in a High Speed Packet Switching Network. ICCC (1986)