Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface.
Yasunobu NakaseYoshikazu MorookaDavid J. PerlmanDaniel J. KolorJae-Myoung ChoiHyun J. ShinTsutomu YoshimuraNaoya WatanabeYoshio MatsudaMasaki KumanoyaMichihiro YamadaPublished in: IEEE J. Solid State Circuits (1999)