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Hyun J. Shin
Publication Activity (10 Years)
Years Active: 1994-2004
Publications (10 Years): 0
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Publications
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Yongsam Moon
,
Young-Soo Park
,
Namhoon Kim
,
Gijung Ahn
,
Hyun J. Shin
,
Deog-Kyoon Jeong
A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link.
IEEE J. Solid State Circuits
39 (5) (2004)
Yasunobu Nakase
,
Yoshikazu Morooka
,
David J. Perlman
,
Daniel J. Kolor
,
Jae-Myoung Choi
,
Hyun J. Shin
,
Tsutomu Yoshimura
,
Naoya Watanabe
,
Yoshio Matsuda
,
Masaki Kumanoya
,
Michihiro Yamada
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface.
IEEE J. Solid State Circuits
34 (4) (1999)
Albert X. Widmer
,
Kevin R. Wrenner
,
Herschel A. Ainspan
,
Ben Parker
,
Pierre Austruy
,
Bernard Brezzo
,
Anne-Marie Haen
,
John F. Ewen
,
Mehmet Soyuer
,
Alain Blanc
,
Jean-Claude Abbiate
,
Alina Deutsch
,
Hyun J. Shin
Single-chip 4×500-MBd CMOS transceiver.
IEEE J. Solid State Circuits
31 (12) (1996)
Hyun J. Shin
,
Dale J. Pearson
,
Scott K. Reynolds
,
Andrew C. Megdanis
,
Sudhir M. Gowda
,
Kevin R. Wrenner
Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications.
IBM J. Res. Dev.
39 (1-2) (1995)
Dale J. Pearson
,
Scott K. Reynolds
,
Andrew C. Megdanis
,
Sudhir M. Gowda
,
Kevin R. Wrenner
,
Michael Immediato
,
Richard L. Galbraith
,
Hyun J. Shin
Digital FIR filters for high speed PRML disk read channels.
IEEE J. Solid State Circuits
30 (12) (1995)
Hyun J. Shin
A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits.
IEEE J. Solid State Circuits
29 (4) (1994)