Yongsam Moon

Publication Activity (10 Years)

Years Active: 1997-2016
Publications (10 Years): 1

Top Topics

False Alarm Probability

Power Dissipation

Charge Coupled Device

Top Venues

IEICE Electron. Express

Publications

Yongsam Moon
Signal detector for 6-Gbps 55-nm CMOS Serial ATA receiver. IEICE Electron. Express 13 (9) (2016)
Seon-Woo Hwang, Yongsam Moon
+1 prescalers based on a shift register and a multi-input NOR gate. IEICE Electron. Express 9 (20) (2012)
Yongsam Moon
A spread-spectrum clock generator for 6-Gbps Serial ATA transceiver. IEICE Electron. Express 7 (13) (2010)
Yongsam Moon
TX rise/fall time control for multi-rate serial link. IEICE Electron. Express 6 (5) (2009)
Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim
4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. ISSCC (2009)
Chul Soo Kim, Joo-Seong Kim, Bai-Sun Kong, Yongsam Moon, Young-Hyun Jun
Presetting pulse-based flip-flop. ISCAS (2008)
Yongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim
A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control. ISSCC (2006)
Yongsam Moon, Sang-Hyun Lee, Daeyun Shim
A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-/spl mu/m CMOS. IEEE J. Solid State Circuits 40 (5) (2005)
Yongsam Moon, Young-Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog-Kyoon Jeong
A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link. IEEE J. Solid State Circuits 39 (5) (2004)
Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong-Joon Lee, Deog-Kyoon Jeong, Wonchan Kim, Young-June Park, Gijung Ahn
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit. IEEE J. Solid State Circuits 37 (12) (2002)
Yongsam Moon, Deog-Kyoon Jeong, Gijung Ahn
A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery. IEEE J. Solid State Circuits 36 (12) (2001)
Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. IEEE J. Solid State Circuits 35 (3) (2000)
Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim
A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. CICC (1999)
Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL. IEEE J. Solid State Circuits 32 (5) (1997)