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An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance.
Yongsam Moon
Jongsang Choi
Kyeongho Lee
Deog-Kyoon Jeong
Min-Kyu Kim
Published in:
IEEE J. Solid State Circuits (2000)
Keyphrases
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wide range
end to end delay
load balancing
signal processing
level set
high levels
piecewise constant
packet loss
power consumption
digital circuits