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4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture.

Yongsam MoonYong-Ho ChoHyun-Bae LeeByung-Hoon JeongSeok-Hun HyunByungchul KimIn-Chul JeongSeong-Young SeoJunho ShinSeok-Woo ChoiHo-Sung SongJung-Hwan ChoiKyehyun KyungYoung-Hyun JunKinam Kim
Published in: ISSCC (2009)
Keyphrases
  • input output
  • real time
  • main memory
  • multi layer
  • polynomial neural networks
  • database systems
  • low cost
  • parallel algorithm
  • file system
  • hardware architecture
  • programmable logic
  • high power
  • linear array
  • processor array