4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture.
Yongsam MoonYong-Ho ChoHyun-Bae LeeByung-Hoon JeongSeok-Hun HyunByungchul KimIn-Chul JeongSeong-Young SeoJunho ShinSeok-Woo ChoiHo-Sung SongJung-Hwan ChoiKyehyun KyungYoung-Hyun JunKinam KimPublished in: ISSCC (2009)