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Bong-Joon Lee
Publication Activity (10 Years)
Years Active: 2002-2009
Publications (10 Years): 0
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Publications
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Jaeha Kim
,
Jeong-Kyoum Kim
,
Bong-Joon Lee
,
Deog-Kyoon Jeong
Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
(12) (2009)
Won-Jun Choe
,
Bong-Joon Lee
,
Jaeha Kim
,
Deog-Kyoon Jeong
,
Gyudong Kim
A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme.
IEEE J. Solid State Circuits
42 (9) (2007)
Jaeha Kim
,
Jeong-Kyoum Kim
,
Bong-Joon Lee
,
Namhoon Kim
,
Deog-Kyoon Jeong
,
Wonchan Kim
A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS.
IEEE J. Solid State Circuits
41 (4) (2006)
Hyung-Rok Lee
,
Moon-Sang Hwang
,
Bong-Joon Lee
,
Young-Deok Kim
,
Dohwan Oh
,
Jaeha Kim
,
Sang-Hyun Lee
,
Deog-Kyoon Jeong
,
Wonchan Kim
A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique.
IEEE J. Solid State Circuits
40 (11) (2005)
Bong-Joon Lee
,
Moon-Sang Hwang
,
Sang-Hyun Lee
,
Deog-Kyoon Jeong
A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization.
IEEE J. Solid State Circuits
38 (11) (2003)
Sang-Hyun Lee
,
Moon-Sang Hwang
,
Youngdon Choi
,
Sungjoon Kim
,
Yongsam Moon
,
Bong-Joon Lee
,
Deog-Kyoon Jeong
,
Wonchan Kim
,
Young-June Park
,
Gijung Ahn
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit.
IEEE J. Solid State Circuits
37 (12) (2002)