Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits.
Jaeha KimJeong-Kyoum KimBong-Joon LeeDeog-Kyoon JeongPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2009)
Keyphrases
- high speed
- analog vlsi
- circuit design
- chip design
- cmos technology
- low power
- power dissipation
- random access memory
- focal plane
- mixed signal
- power supply
- low cost
- vlsi circuits
- inductive learning
- single chip
- delay insensitive
- power consumption
- multi channel
- knowledge representation
- logic circuits
- communication systems
- quantum computing
- cmos image sensor