A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit.
Sang-Hyun LeeMoon-Sang HwangYoungdon ChoiSungjoon KimYongsam MoonBong-Joon LeeDeog-Kyoon JeongWonchan KimYoung-June ParkGijung AhnPublished in: IEEE J. Solid State Circuits (2002)
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