A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-/spl mu/m CMOS.
Yongsam MoonSang-Hyun LeeDaeyun ShimPublished in: IEEE J. Solid State Circuits (2005)
Keyphrases
- high speed
- low power
- spl times
- cmos technology
- ultra low power
- frequency response
- data acquisition
- ultra wide band
- circuit design
- phase locked loop
- focal plane
- power dissipation
- wireless systems
- analog vlsi
- real time
- development environment
- low cost
- logic circuits
- low voltage
- delay insensitive
- vlsi circuits
- parallel processing
- data collection