Yasuto Kuroda

Publication Activity (10 Years)

Years Active: 2005-2016
Publications (10 Years): 3

Top Topics

Top Venues

IEICE Trans. Commun.

Publications

Hideaki Furukawa, Hiroaki Harai, Yasuto Kuroda, Yuji Yano, Shoji Koyama
Demonstration of 100 Gbps optical packet switching using header processor based on 48-bit longest prefix matching. Photonic Netw. Commun. 31 (3) (2016)
Masami Nawa, Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka
Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure. CCNC (2016)
Hideaki Furukawa, Hiroaki Harai, Yasuto Kuroda, Shoji Koyama
Demonstrating 100 Gbps optical packet switching using 16-bit longest prefix matching forwarding engine. ONDM (2015)
Hideaki Furukawa, Takaya Miyazawa, Hiroaki Harai, Yasuto Kuroda, Shoji Koyama, Shin'ichi Arakawa, Masayuki Murata
Development of onboard LPM-based header processing and reactive link selection for optical packet and circuit integrated networks. ICC (2014)
Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Kazunari Inoue, Ikuo Oka
A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application. IEICE Trans. Electron. (8) (2013)
Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue
Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS. IEICE Trans. Commun. (7) (2013)
Sou Koyano, Shingo Ata, Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Kazunari Inoue, Ikuo Oka
A study on micro level traffic prediction for energy-aware routers. ACM SIGOPS Oper. Syst. Rev. 47 (3) (2013)
Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. IEEE J. Solid State Circuits 48 (11) (2013)
Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka
2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving. CCNC (2013)
Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka
FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine. IEICE Trans. Commun. (7) (2012)
Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki
A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application. CICC (2012)
Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue
Deterministic High Density Packet-Buffer System for Low Cost Network Systems. AINA (2012)
Yuji Yano, Hisashi Iwamoto, Yasuto Kuroda, Shiro Ohtani, Shingo Ata, Kazunari Inoue
A slice structure using the management of network traffic prediction for green IT. HPSR (2012)
Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka
Hardware implementation of fast forwarding engine using standard memory and dedicated circuit. ICECS (2010)
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Trans. Electron. (9) (2008)
Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS (2007)
Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Trans. Inf. Syst. (1) (2007)
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Trans. Inf. Syst. (8) (2007)
Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) (2005)