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Hardware implementation of fast forwarding engine using standard memory and dedicated circuit.
Kazuya Zaitsu
Koji Yamamoto
Yasuto Kuroda
Kazunari Inoue
Shingo Ata
Ikuo Oka
Published in:
ICECS (2010)
Keyphrases
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hardware implementation
memory management
shift register
efficient implementation
processing elements
software implementation
high speed
fpga implementation
hardware design
hardware architecture
signal processing
image processing algorithms
field programmable gate array
evolvable hardware
dedicated hardware
memory requirements
fpga device
image binarization
neural network
pipeline architecture