Hardware implementation of fast forwarding engine using standard memory and dedicated circuit.
Kazuya ZaitsuKoji YamamotoYasuto KurodaKazunari InoueShingo AtaIkuo OkaPublished in: ICECS (2010)
Keyphrases
- hardware implementation
- memory management
- shift register
- efficient implementation
- processing elements
- software implementation
- high speed
- fpga implementation
- hardware design
- hardware architecture
- signal processing
- image processing algorithms
- field programmable gate array
- evolvable hardware
- dedicated hardware
- memory requirements
- fpga device
- image binarization
- neural network
- pipeline architecture