Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor.
Takeshi KumakiMasakatsu IshizakiTetsushi KoideHans Jürgen MattauschYasuto KurodaTakayuki GyohtenHideyuki NodaKatsumi DosakaKazutami ArimotoKazunori SaitoPublished in: IEICE Trans. Electron. (2008)
Keyphrases
- processing elements
- single instruction multiple data
- content addressable memory
- massively parallel
- multimedia
- parallel architectures
- parallel computers
- hardware architecture
- parallel architecture
- associative memory
- parallel processors
- random access
- level parallelism
- parallel processing
- image processing algorithms
- real time
- hardware implementation
- embedded systems
- single processor
- parallel computing
- singular value decomposition
- linear algebra
- field programmable gate array
- parallel implementation
- highly parallel
- neural network
- efficient implementation
- high performance computing
- multithreading
- high speed
- hardware design
- shared memory
- computer architecture
- instruction set
- fine grained
- processor array