Haruo Shimamoto

Publication Activity (10 Years)

Years Active: 2009-2021
Publications (10 Years): 11

Top Topics

Protection Scheme

Integrated Circuit

Malicious Nodes

Top Venues

Microelectron. Reliab.

IEICE Electron. Express

Publications

Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Analysis and evaluation of noise coupling between through-silicon-vias. IEICE Electron. Express 18 (11) (2021)
Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Landside capacitor efficacy among multi-chip-module using Si-interposer. IEICE Electron. Express 18 (9) (2021)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55 (10) (2020)
Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC (2019)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC (2019)
Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. 3DIC (2019)
Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 79 (2017)
Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
Validation of TSV thermo-mechanical simulation by stress measurement. Microelectron. Reliab. 59 (2016)
Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura
Wet cleaning process for high-yield via-last TSV formation. 3DIC (2016)
Wei Feng, Bui Thanh Tung, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
Fabrication and stress analysis of annular-trench-isolated TSV. Microelectron. Reliab. 63 (2016)
Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 67 (2016)
Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
Analysis of thermal stress distribution for TSV with novel structure. 3DIC (2014)
Kosuke Kitaichi, Haruo Shimamoto, Chuichi Miyazaki, Yoshiyuki Abe, Sigeaki Saito, Shoji Yasunaga
Development of high accuracy wafer thinning and pickup technology for thin wafer. 3DIC (2011)
Chuichi Miyazaki, Haruo Shimamoto, Toshihide Uematsu, Yoshiyuki Abe, Kosuke Kitaichi, Tadahiro Morifuji, Shoji Yasunaga
Development of high accuracy wafer thinning and pickup technology for thin wafer. 3DIC (2010)
Chuichi Miyazaki, Haruo Shimamoto, Toshihide Uematsu, Yoshiyuki Abe
Development of wafer thinning and dicing technology for thin wafer. 3DIC (2009)