COOL interconnect low power interconnection technology for scalable 3D LSI design.
Marco ChacinHiroyuki UchidaMichiya HagimotoTakashi MiyazakiTakeshi OhkawaRimon IkenoYukoh MatsumotoFumito ImuraMotohiro SuzukiKatsuya KikuchiHiroshi NakagawaMasahiro AoyagiPublished in: COOL Chips (2011)
Keyphrases
- low power
- gate array
- high speed
- cmos technology
- power dissipation
- power consumption
- single chip
- low cost
- low power consumption
- nm technology
- logic circuits
- vlsi architecture
- wireless transmission
- digital signal processing
- vlsi circuits
- mixed signal
- cmos image sensor
- power reduction
- ultra low power
- hardware and software
- real time
- high power
- computer systems
- design process
- parallel processing