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High level synthesis of ROS protocol interpretation and communication circuit for FPGA.
Takeshi Ohkawa
Yuhei Sugata
Harumi Watanabe
Nobuhiko Ogura
Kanemitsu Ootsu
Takashi Yokota
Published in:
RoSE@ICSE (2019)
Keyphrases
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high level synthesis
high speed
parallel architecture
communication protocol
communication protocols
tcp ip
data acquisition
group communication
low cost
communication networks
multi party
field programmable gate array
fault tolerance
power reduction
gate array
hardware design
parallel processing
fault tolerant