STRAIGHT: Hazardless Processor Architecture Without Register Renaming.
Hidetsugu IrieToru KoizumiAkifumi FukudaSeiya AkakiSatoshi NakaeYutaro BesshoRyota ShioyaTakahiro NotsuKatsuhiro YodaTeruo IshiharaShuichi SakaiPublished in: MICRO (2018)
Keyphrases
- multi processor
- instruction set
- parallel architecture
- management system
- high speed
- software architecture
- systolic array
- industry standard
- parallel processing
- multi core processors
- real time
- database
- design methodology
- single chip
- memory management
- multithreading
- straight line
- layered architecture
- data sets
- multiprocessor systems
- computation intensive