Akashi Satoh

Publication Activity (10 Years)

Years Active: 1997-2022
Publications (10 Years): 9

Top Topics

Countermeasures

Fpga Implementation

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEICE Trans. Inf. Syst.

J. Inf. Process.

Publications

Mitsuki Terada, Akashi Satoh
Development of Hornet Detection Camera System for Smart Beekeeping. GCCE (2022)
Kaori Uehara, Hiromichi Ikeda, Akashi Satoh
Fertilizer Management System for A Compact Hydroponic Planter. GCCE (2019)
Akashi Satoh
A Hydroponic Planter System to enable an Urban Agriculture Service Industry. GCCE (2018)
Masato Matsubayashi, Hendra Guntur, Akashi Satoh
Security evaluation of cryptographic modules against side-channel attack using a biased data set. GCCE (2017)
Tomohiro Nishimura, Yuji Okuyama, Ayaka Matsushita, Hiromichi Ikeda, Akashi Satoh
A compact hardware design of a sensor module for hydroponics. GCCE (2017)
Tomohiro Nishimura, Yuji Okuyama, Akashi Satoh
High-accuracy and low-cost sensor module for hydroponic culture system. GCCE (2016)
Makiko Kosugi, Akashi Satoh
GPGPU software implementation of authenticated encryption algorithm Minalpher. GCCE (2016)
Yu Nomata, Masato Matsubayashi, Kohei Sawada, Akashi Satoh
Comparison of side-channel attack on cryptographic cirucits between old and new technology FPGAs. GCCE (2016)
Masato Matsubayashi, Akashi Satoh, Jun Ishii
Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit. GCCE (2016)
Makiko Kosug, Masahiro Yasuda, Akashi Satoh
FPGA implementation of authenticated encryption algorithm Minalpher. GCCE (2015)
Masato Matsubayashi, Akashi Satoh
Side-channel Attack user reference architecture board SAKURA-W for security evaluation of IC card. GCCE (2015)
Hendra Guntur, Jun Ishii, Akashi Satoh
Side-channel AttacK User Reference Architecture board SAKURA-G. GCCE (2014)
Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh, Shin-ichi Kawamura, Kazukuni Kobara
Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays. J. Inf. Process. 22 (2) (2014)
Tatsuya Honda, Hendra Guntur, Akashi Satoh
FPGA implementation of new standard hash function Keccak. GCCE (2014)
Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh
Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption. IEICE Trans. Inf. Syst. (11) (2013)
Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2012)
Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Koçabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates. IEEE Trans. Very Large Scale Integr. Syst. 20 (5) (2012)
Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takeshi Sugawara, Yoshiki Kayano, Takafumi Aoki, Shigeki Minegishi, Akashi Satoh, Hideaki Sone, Hiroshi Inoue
Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current. IEICE Trans. Electron. (6) (2012)
Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
An on-chip glitchy-clock generator for testing fault injection attacks. J. Cryptogr. Eng. 1 (4) (2011)
Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST (2011)
Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
High-Performance Architecture for Concurrent Error Detection for AES Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2011)
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 19 (7) (2011)
Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh
Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function. ReConFig (2011)
Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir
Comparative Power Analysis of Modular Exponentiation Algorithms. IEEE Trans. Computers 59 (6) (2010)
Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Akashi Satoh, Tsutomu Matsumoto
A Design Methodology for a DPA-Resistant Circuit with RSL Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. ReConFig (2010)
Kazuyuki Kobayashi, Jun Ikegami, Kazuo Sakiyama, Kazuo Ohta, Miroslav Knezevic, Ünal Koçabas, Junfeng Fan, Ingrid Verbauwhede, Eric Xu Guo, Shin'ichiro Matsuo, Sinan Huang, Leyla Nazhandali, Akashi Satoh
Prototyping Platform for Performance Evaluation of SHA-3 Candidates. HOST (2010)
Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
Profiling attack using multivariate regression analysis. IEICE Electron. Express 7 (15) (2010)
Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
Hardware Implementations of Hash Function Luffa. HOST (2010)
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
Evaluation of Simple/Comparative Power Analysis against an RSA ASIC Implementation. ISCAS (2009)
Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
Differential power analysis of AES ASIC implementations with various S-box circuits. ECCTD (2009)
Takeshi Sugawara, Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Akashi Satoh
Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules. WISA (2009)
Akashi Satoh, Takeshi Sugawara, Takafumi Aoki
High-Performance Hardware Architectures for Galois Counter Mode. IEEE Trans. Computers 58 (7) (2009)
Akashi Satoh, Nicolas Sklavos
Compact and High-speed Hardware Architectures for Hash Function Tiger. ISCAS (2009)
Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
Development of side-channel attack standard evaluation environment. ECCTD (2009)
Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh
Is the differential frequency-based attack effective against random delay insertion? SiPS (2009)
Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. CHES (2009)
Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
High-Performance Concurrent Error Detection Scheme for AES Hardware. CHES (2008)
Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir
Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs. CHES (2008)
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
Enhanced power analysis attack using chosen message against RSA hardware implementations. ISCAS (2008)
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
Chosen-message SPA attacks against FPGA-based RSA hardware implementations. FPL (2008)
Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. FPL (2008)
Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
Enhanced Correlation Power Analysis Using Key Screening Technique. ReConFig (2008)
Naofumi Homma, Sei Nagashima, Takeshi Sugawara, Takafumi Aoki, Akashi Satoh
A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2008)
Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
High-performance ASIC implementations of the 128-bit block cipher CLEFIA. ISCAS (2008)
Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda
Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems. IWSEC (2008)
Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool. WISA (2008)
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
Systematic design of high-radix Montgomery multipliers for RSA processors. ICCD (2008)
Akashi Satoh
ASIC hardware implementations for 512-bit hash function Whirlpool. ISCAS (2008)
Akashi Satoh
High-Speed Parallel Hardware Architecture for Galois Counter Mode. ISCAS (2007)
Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. ISCAS (2007)
Akashi Satoh, Takeshi Sugawara, Takafumi Aoki
High-Speed Pipelined Hardware Architecture for Galois Counter Mode. ISC (2007)
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. ISCAS (2007)
Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh
DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. ISCAS (2007)
Akashi Satoh, Tadanobu Inoue
ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS. Integr. 40 (1) (2007)
Akashi Satoh
High-speed hardware architectures for authenticated encryption mode GCM. ISCAS (2006)
Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh
High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. CHES (2006)
Akashi Satoh
Hardware Architecture and Cost Estimates for Breaking SHA-1. ISC (2005)
Akashi Satoh, Tadanobu Inoue
ASIC-Hardware-Focused Comparison for Hash Functions MD5, RIPEMD-160, and SHS. ITCC (1) (2005)
Sumio Morioka, Akashi Satoh
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. IEEE Trans. Very Large Scale Integr. Syst. 12 (7) (2004)
Shigenori Shimizu, Hiroshi Ishikawa, Akashi Satoh, Toru Aihara
On-demand design service innovations. IBM J. Res. Dev. 48 (5-6) (2004)
Akashi Satoh, Sumio Morioka
Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. CHES (2003)
Akashi Satoh, Kohji Takano
A Scalable Dual-Field Elliptic Curve Cryptographic Processor. IEEE Trans. Computers 52 (4) (2003)
Akashi Satoh, Sumio Morioka
Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. ISC (2003)
Sumio Morioka, Akashi Satoh
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. ICCD (2002)
Akashi Satoh, Sumio Morioka
Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. ISC (2002)
Sumio Morioka, Akashi Satoh
An Optimized S-Box Circuit Architecture for Low Power AES Design. CHES (2002)
Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh
A Compact Rijndael Hardware Architecture with S-Box Optimization. ASIACRYPT (2001)
Akashi Satoh, Nobuyuki Ooba, Kohji Takano, Edward D'Avignon
High-Speed MARS Hardware. AES Candidate Conference (2000)
Akashi Satoh, Yoshinao Kobayashi, Hideto Niijima, Nobuyuki Ooba, Seiji Munetoh, Sadamichi Sone
A High-Speed Small RSA Encryption LSI with Low Power Dissipation. ISW (1997)
W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD (1997)