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High-Performance Architecture for Concurrent Error Detection for AES Processors.
Takeshi Sugawara
Naofumi Homma
Takafumi Aoki
Akashi Satoh
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2011)
Keyphrases
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error detection
error correction
parallel computers
error recovery
signal processor
data cleansing
parallel architecture
embedded processors
fault isolation
error correcting
error resilient
distributed memory
fault tolerance
parallel processing
parallel algorithm
neural network
error control
array processor