Minoru Saeki

Publication Activity (10 Years)

Years Active: 2004-2016
Publications (10 Years): 1

Top Topics

Attack Detection

Countermeasures

Top Venues

IACR Cryptol. ePrint Arch.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki
Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki
Two Operands of Multipliers in Side-Channel Attack. COSADE (2015)
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki
Two Operands of Multipliers in Side-Channel Attack. IACR Cryptol. ePrint Arch. 2015 (2015)
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
On measurable side-channel leaks inside ASIC design primitives. J. Cryptogr. Eng. 4 (1) (2014)
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
On Measurable Side-Channel Leaks inside ASIC Design Primitives. IACR Cryptol. ePrint Arch. 2013 (2013)
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
On Measurable Side-Channel Leaks Inside ASIC Design Primitives. CHES (2013)
Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Tsutomu Matsumoto
How to Decide Selection Functions for Power Analysis: From the Viewpoint of Hardware Architecture of Block Ciphers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2011)
Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Akashi Satoh, Tsutomu Matsumoto
A Design Methodology for a DPA-Resistant Circuit with RSL Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. CHES (2009)
Daisuke Suzuki, Minoru Saeki
An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2008)
Minoru Saeki, Daisuke Suzuki
Security Evaluations of MRSL and DRSL Considering Signal Delays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2008)
Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2007)
Minoru Saeki, Daisuke Suzuki, Tetsuya Ichikawa
Leakage Analysis of DPA Countermeasures at the Logic Level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2007)
Daisuke Suzuki, Minoru Saeki
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. CHES (2006)
Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
DPA Leakage Models for CMOS Logic Circuits. CHES (2005)
Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
Random Switching Logic: A Countermeasure against DPA based on Transition Probability. IACR Cryptol. ePrint Arch. 2004 (2004)