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DPA Leakage Models for CMOS Logic Circuits.

Daisuke SuzukiMinoru SaekiTetsuya Ichikawa
Published in: CHES (2005)
Keyphrases
  • logic circuits
  • probabilistic model
  • low power
  • low cost
  • high speed
  • peer to peer
  • pattern recognition
  • massively parallel
  • tunnel diode