High-Speed Pipelined Hardware Architecture for Galois Counter Mode.

Akashi Satoh Takeshi Sugawara Takafumi Aoki

Published in: ISC (2007)

Keyphrases

hardware architecture
high speed
hardware implementation
hardware architectures
low power
formal concept analysis
associative memory
data flow
field programmable gate array
formal concepts
real time
processing elements
low cost
computer vision
image quality
high level
information systems