An Optimized S-Box Circuit Architecture for Low Power AES Design.

Sumio Morioka Akashi Satoh

Published in: CHES (2002)

Keyphrases

low power
cmos technology
vlsi architecture
logic circuits
high speed
power dissipation
mixed signal
power consumption

gate array
s box
nm technology
power reduction
low cost
single chip
low power consumption
vlsi circuits

circuit design
block cipher
vlsi implementation
digital signal processing
low voltage
design methodology
image sensor

multi channel
delay insensitive
design process
parallel processing
real time
ultra low power
data flow