Sumio Morioka

Publication Activity (10 Years)

Years Active: 1994-2023
Publications (10 Years): 10

Top Topics

Hardware Architecture

Mass Spectrometry Data

Secure Communication

Top Venues

IACR Cryptol. ePrint Arch.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Maki Yoshida, Sumio Morioka, Satoshi Obana
Secure Communication via GNSS-based Key Synchronization. WIPHAL (2023)
Maki Yoshida, Sumio Morioka, Satoshi Obana
On Cryptographic Algorithms and Key Length for Delayed Disclosure Authentication of GNSS. ICL-GNSS (2022)
Rei Ueno, Naofumi Homma, Sumio Morioka, Takafumi Aoki
A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware. IEEE Des. Test 38 (3) (2021)
Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69 (4) (2020)
Kosei Sakamoto, Kazuhiko Minematsu, Nao Shibata, Maki Shigeri, Hiroyasu Kubo, Yuki Funabiki, Andrey Bogdanov, Sumio Morioka, Takanori Isobe
Tweakable TWINE: Building a Tweakable Block Cipher on Generalized Feistel Structure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2020)
Kosei Sakamoto, Kazuhiko Minematsu, Nao Shibata, Maki Shigeri, Hiroyasu Kubo, Yuki Funabiki, Andrey Bogdanov, Sumio Morioka, Takanori Isobe
Tweakable TWINE: Building a Tweakable Block Cipher on Generalized Feistel Structure. IWSEC (2019)
Rei Ueno, Naofumi Homma, Takafumi Aoki, Sumio Morioka
Hierarchical Formal Verification Combining Algebraic Transformation with PPRM Expansion and Its Application to Masked Cryptographic Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Rei Ueno, Naofumi Homma, Sumio Morioka, Takafumi Aoki
Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme. DATE (2017)
Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. IACR Cryptol. ePrint Arch. 2016 (2016)
Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. CHES (2016)
Kotaro Okamoto, Naofumi Homma, Takafumi Aoki, Sumio Morioka
A hierarchical formal approach to verifying side-channel resistant cryptographic processors. HOST (2014)
Tetsu Iwata, Kazuhiko Minematsu, Jian Guo, Sumio Morioka
CLOC: Authenticated Encryption for Short Input. FSE (2014)
Tetsu Iwata, Kazuhiko Minematsu, Jian Guo, Sumio Morioka
CLOC: Authenticated Encryption for Short Input. IACR Cryptol. ePrint Arch. 2014 (2014)
Tomoyasu Suzaki, Kazuhiko Minematsu, Sumio Morioka, Eita Kobayashi
$\textnormal{\textsc{TWINE}}$ : A Lightweight Block Cipher for Multiple Platforms. Selected Areas in Cryptography (2012)
Sumio Morioka, Toshiyuki Isshiki, Satoshi Obana, Yuichi Nakamura, Kazue Sako
Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology. HOST (2011)
Sumio Morioka, Akashi Satoh
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. IEEE Trans. Very Large Scale Integr. Syst. 12 (7) (2004)
Akashi Satoh, Sumio Morioka
Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. CHES (2003)
Akashi Satoh, Sumio Morioka
Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. ISC (2003)
Sumio Morioka, Akashi Satoh
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. ICCD (2002)
Akashi Satoh, Sumio Morioka
Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. ISC (2002)
Sumio Morioka, Akashi Satoh
An Optimized S-Box Circuit Architecture for Low Power AES Design. CHES (2002)
Sumio Morioka, Yasunao Katayama, Toshiyuki Yamane
). CAV (2001)
Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh
A Compact Rijndael Hardware Architecture with S-Box Optimization. ASIACRYPT (2001)
Yasunao Katayama, Yasushi Negishi, Sumio Morioka
Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs. DFT (2000)
Yasunao Katayama, Sumio Morioka
One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems. DSN (2000)
Yasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu
Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention. DFT (1999)
Sumio Morioka, Yasunao Katayama
Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder. ICCD (1999)
Junji Kitamichi, Sumio Morioka, Teruo Higashino, Kenichi Taniguchi
Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach. TPCD (1994)