A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation.
Rei UenoSumio MoriokaNaofumi HommaTakafumi AokiPublished in: CHES (2016)
Keyphrases
- high throughput
- hardware architecture
- hardware implementation
- microarray
- systems biology
- genome wide
- biological data
- hardware architectures
- dna sequencing
- low latency
- proteomic data
- efficient implementation
- mass spectrometry data
- neural network
- genomic data
- real time
- protein protein interactions
- associative memory
- high speed