High-Performance Concurrent Error Detection Scheme for AES Hardware.
Akashi SatohTakeshi SugawaraNaofumi HommaTakafumi AokiPublished in: CHES (2008)
Keyphrases
- detection scheme
- error detection
- hardware and software
- low cost
- scientific computing
- error rate
- signal processor
- real time
- advanced encryption standard
- embedded processors
- hardware implementation
- image processing
- parallel hardware
- single chip
- computing power
- massively parallel
- high efficiency
- error bounds
- secret key
- image sensor
- low latency
- error analysis
- mutual exclusion
- low power
- cost effective
- computer systems