Daisuke Fujimoto

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 22

Top Topics

Integrated Circuit

Pearson Correlation Coefficient

Fault Injection

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IACR Cryptol. ePrint Arch.

Publications

Junichi Sakamoto, Daisuke Fujimoto, Riku Anzai, Naoki Yoshida, Tsutomu Matsumoto
High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications. IEEE Trans. Very Large Scale Integr. Syst. 32 (8) (2024)
Hikaru Nishiyama, Daisuke Fujimoto, Yu-ichi Hayashi
Remote Fault Injection Attack against Cryptographic Modules via Intentional Electromagnetic Interference from an Antenna. ASHES@CCS (2023)
Junichi Sakamoto, Shungo Hayashi, Daisuke Fujimoto, Tsutomu Matsumoto
Constructing software countermeasures against instruction manipulation attacks: an approach based on vulnerability evaluation using fault simulator. Clust. Comput. 25 (4) (2022)
Shinichi Kawamura, Yuichi Komano, Hideo Shimizu, Saki Osuka, Daisuke Fujimoto, Yu-ichi Hayashi, Kentaro Imafuku
Efficient Algorithms for Sign Detection in RNS Using Approximate Reciprocals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2021)
Junichi Sakamoto, Shungo Hayashi, Daisuke Fujimoto, Tsutomu Matsumoto
How to Code Data Integrity Verification Secure Against Single-Spot-Laser-Induced Instruction Manipulation Attacks. AICCSA (2020)
Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto
Laser-Induced Controllable Instruction Replacement Fault Attack. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2020)
Jurica Kundrata, Daisuke Fujimoto, Yu-ichi Hayashi, Adrijan Baric
Comparison of Pearson correlation coefficient and distance correlation in Correlation Power Analysis on Digital Multiplier. MIPRO (2020)
Junichi Sakamoto, Yusuke Nagahama, Daisuke Fujimoto, Yota Okuaki, Tsutomu Matsumoto
Low-Latency Pairing Processor Architecture Using Fully-Unrolled Quotient Pipelining Montgomery Multiplier. AsianHOST (2019)
Masahiro Kinugawa, Daisuke Fujimoto, Yu-ichi Hayashi
Electromagnetic Information Extortion from Electronic Devices Using Interceptor and Its Countermeasure. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019 (4) (2019)
Arthur Beckers, Masahiro Kinugawa, Yu-ichi Hayashi, Daisuke Fujimoto, Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede
Design Considerations for EM Pulse Fault Injection. CARDIS (2019)
Daisuke Fujimoto, Takashi Narimatsu, Yu-ichi Hayashi
Fundamental Study on the Effects of Connector Torque Value on the Change of Inductance at the Contact Boundary. IEICE Trans. Electron. (9) (2019)
Daisuke Fujimoto, Shota Nin, Yu-ichi Hayashi, Noriyuki Miura, Makoto Nagata, Tsutomu Matsumoto
A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Takafumi Aoki
Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks. J. Cryptol. 30 (2) (2017)
Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, Naofumi Homma, Yu-ichi Hayashi, Kazuo Sakiyama
Protecting cryptographic integrated circuits with side-channel information. IEICE Electron. Express 14 (2) (2017)
Daisuke Fujimoto, Shivam Bhasin, Makoto Nagata, Jean-Luc Danger
A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version). IACR Cryptol. ePrint Arch. 2016 (2016)
Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto
Laser irradiation on EEPROM sense amplifiers enhances side-channel leakage of read bits. AsianHOST (2016)
Daisuke Fujimoto, Yusuke Nagahama, Tsutomu Matsumoto
How to design hardware prime field multipliers for bilinear pairing. ISOCC (2016)
Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. ASP-DAC (2015)
Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. IEEE J. Solid State Circuits 50 (11) (2015)
Daisuke Fujimoto, Makoto Nagata, Shivam Bhasin, Jean-Luc Danger
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. ASP-DAC (2015)
Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki
EM attack sensor: concept, circuit, and design-automation methodology. DAC (2015)
Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. IEEE Trans. Very Large Scale Integr. Syst. 23 (8) (2015)
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor. CHES (2014)
Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Shivam Bhasin, Jean-Luc Danger
Side-channel leakage on silicon substrate of CMOS cryptographic chip. HOST (2014)
Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. (4) (2014)
Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. ATS (2014)
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor. IACR Cryptol. ePrint Arch. 2014 (2014)
Noriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. A-SSCC (2014)
Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. VLSIC (2014)
Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS@DATE (2014)
Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC (2014)
Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST (2011)
Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata
An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. IEICE Trans. Electron. (6) (2010)
Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata
A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. CICC (2009)
Sadao Kawamura, Katsuya Kanaoka, Yuichiro Nakayama, Jinwoo Jeon, Daisuke Fujimoto
Improvement of passive elements for wearable haptic displays. ICRA (2003)