Low-Latency Pairing Processor Architecture Using Fully-Unrolled Quotient Pipelining Montgomery Multiplier.
Junichi SakamotoYusuke NagahamaDaisuke FujimotoYota OkuakiTsutomu MatsumotoPublished in: AsianHOST (2019)
Keyphrases
- low latency
- xilinx virtex
- hardware implementation
- high speed
- fpga implementation
- real time
- integer arithmetic
- parallel processing
- high bandwidth
- smart card
- parallel architecture
- high throughput
- hardware architecture
- low end
- highly efficient
- field programmable gate array
- virtual machine
- stream processing
- efficient implementation