Sign in
A 6-bit arbitrary digital noise emulator in 65nm CMOS technology.
Tetsuro Matsuno
Daisuke Fujimoto
Daisuke Kosaka
Naoyuki Hamanishi
Ken Tanabe
Masazumi Shiochi
Makoto Nagata
Published in:
CICC (2009)
Keyphrases
</>
cmos technology
spl times
mixed signal
low power
power consumption
parallel processing
low voltage
low cost
cmos image sensor
power dissipation
silicon on insulator
flip flops
high speed
image sensor
missing data
image formation
signal to noise ratio
pattern recognition