A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement.
Daisuke FujimotoMakoto NagataShivam BhasinJean-Luc DangerPublished in: ASP-DAC (2015)
Keyphrases
- ibm power processor
- low cost
- chip design
- trusted computing
- vlsi implementation
- multithreading
- design methodology
- error resilience
- programmable logic
- single chip
- trust management
- host computer
- public key infrastructure
- measurement error
- memory subsystem
- power management
- trust relationships
- instruction set
- security services
- data acquisition
- hardware software co design
- intrusion detection
- measurement model
- information security
- access control
- ibm zenterprise
- power consumption
- security policies
- high speed
- hardware and software
- computational power
- computer systems
- application specific integrated circuits
- silicon on insulator
- embedded systems
- security issues
- evolvable hardware
- privacy concerns
- computing platform
- circuit design
- cloud computing
- physical design
- random number generator
- trust model
- hardware implementation
- field programmable gate array
- real time
- operating system