A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version).
Daisuke FujimotoShivam BhasinMakoto NagataJean-Luc DangerPublished in: IACR Cryptol. ePrint Arch. (2016)
Keyphrases
- ibm power processor
- trusted computing
- chip design
- low cost
- measurement noise
- vlsi implementation
- measurement errors
- security services
- trust management
- hardware and software
- multithreading
- error resilience
- hardware software co design
- single chip
- design methodology
- programmable logic
- power consumption
- memory subsystem
- host computer
- trust relationships
- measurement error
- real time
- trust negotiation
- security policies
- signal to noise ratio
- circuit design
- power management
- public key infrastructure
- hardware implementation
- security protocols
- access control
- instruction set
- trust model
- security issues
- security requirements
- intrusion detection
- evolvable hardware
- information security
- field programmable gate array
- image sensor
- test cases
- power dissipation
- reconfigurable hardware
- high speed
- computational power
- ibm zenterprise
- massively parallel
- random number generator
- privacy concerns
- key management
- computer systems
- security mechanisms
- hardware software
- cloud computing
- memory access
- operating system