Matthew R. Wordeman

Publication Activity (10 Years)

Years Active: 1992-2016
Publications (10 Years): 2

Top Topics

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

Publications

Michael Scheuermann, Shurong Tian, Raphael Robertazzi, Matthew R. Wordeman, C. Bergeron, H. Jacobson, Phillip J. Restle, Joel Silberman, Christy Tyberg
Thermal analysis of multi-layer functional 3D logic stacks. 3DIC (2016)
Toshiaki Kirihata, John Golz, Matthew R. Wordeman, Pooja Batra, Gary W. Maier, Norman Robson, Troy L. Graves-abe, Daniel Berger, Subramanian S. Iyer
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (3) (2016)
Liang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier
A shorted global clock design for multi-GHz 3D stacked chips. VLSIC (2012)
Steven J. Koester, Albert M. Young, Roy R. Yu, Sampath Purushothaman, Kuan-Neng Chen, Douglas C. La Tulipe Jr., Narender Rana, Leathen Shi, Matthew R. Wordeman, Edmund J. Sprogis
Wafer-level 3D integration technology. IBM J. Res. Dev. 52 (6) (2008)
Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman
cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. IEEE J. Solid State Circuits 35 (5) (2000)
Osamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. IEEE J. Solid State Circuits 35 (11) (2000)
Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman
, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. IEEE J. Solid State Circuits 34 (11) (1999)
Toshiaki Kirihata, Martin Gall, Kohji Hosokawa, Jean-Marc Dortu, Hing Wong, Peter Pfefferl, Brian L. Ji, Oliver Weinfurtner, John K. DeBrosse, Hartmud Terletzki, Manfred Selz, Wayne Ellis, Matthew R. Wordeman, Oliver Kiehl
, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. IEEE J. Solid State Circuits 33 (11) (1998)
Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik
Flexible test mode approach for 256-Mb DRAM. IEEE J. Solid State Circuits 32 (10) (1997)
W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD (1997)
Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii
256 Mb DRAM with ×32 both-ends DQ. IEEE J. Solid State Circuits 31 (4) (1996)
Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao
Fault-tolerant designs for 256 Mb DRAM. IEEE J. Solid State Circuits 31 (4) (1996)
Charles W. Koburger III, William F. Clark, James W. Adkisson, Eric Adler, Paul E. Bakeman, Albert S. Bergendahl, Alan B. Botula, W. Chang, Bijan Davari, John H. Givens, Howard H. Hansen, Steven J. Holmes, David V. Horak, Chung Hon Lam, Jerome B. Lasky, Stephen E. Luce, Randy W. Mann, Glen L. Miles, James S. Nakos, Edward J. Nowak, Ghavam Shahidi, Yuan Taur, Francis R. White, Matthew R. Wordeman
A half-micron CMOS logic generation. IBM J. Res. Dev. 39 (1-2) (1995)
Wai Lee, Steven E. Laux, Massimo V. Fischetti, Giorgio Baccarani, Antonio Gnudi, Johannes M. C. (Hans) Stork, Jack A. Mandelman, Emmanuel F. Crabbé, Matthew R. Wordeman, Farouk Odeh
Numerical modeling of advanced semiconductor devices. IBM J. Res. Dev. 36 (2) (1992)