1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro.
Osamu TakahashiSang H. DhongManabu OhkuboShohji OnishiRobert H. DennardRobert HannonScott CrowderSubramanian S. IyerMatthew R. WordemanBijan DavariWilliam B. WeinbergerNaoaki AokiPublished in: IEEE J. Solid State Circuits (2000)