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1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro.

Osamu TakahashiSang H. DhongManabu OhkuboShohji OnishiRobert H. DennardRobert HannonScott CrowderSubramanian S. IyerMatthew R. WordemanBijan DavariWilliam B. WeinbergerNaoaki Aoki
Published in: IEEE J. Solid State Circuits (2000)
Keyphrases
  • main memory
  • embedded systems
  • access control
  • dynamic random access memory
  • random access
  • metadata
  • index structure
  • data flow
  • high density
  • network simulator