Login / Signup
Naoaki Aoki
Publication Activity (10 Years)
Years Active: 1998-2000
Publications (10 Years): 0
</>
Publications
</>
Stephen D. Posluszny
,
Naoaki Aoki
,
David Boerstler
,
Paula K. Coulman
,
Sang H. Dhong
,
Brian K. Flachs
,
H. Peter Hofstee
,
Nobuo Kojima
,
Ohsang Kwon
,
Kyung T. Lee
,
David Meltzer
,
Kevin J. Nowka
,
J. Park
,
J. Peter
,
Joel Silberman
,
Osamu Takahashi
,
Paul Villarrubia
"Timing closure by design, " a high frequency microprocessor design methodology.
DAC
(2000)
Osamu Takahashi
,
Sang H. Dhong
,
Manabu Ohkubo
,
Shohji Onishi
,
Robert H. Dennard
,
Robert Hannon
,
Scott Crowder
,
Subramanian S. Iyer
,
Matthew R. Wordeman
,
Bijan Davari
,
William B. Weinberger
,
Naoaki Aoki
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro.
IEEE J. Solid State Circuits
35 (11) (2000)
Osamu Takahashi
,
Naoaki Aoki
,
Joel Silberman
,
Sang H. Dhong
A 1-GHz logic circuit family with sense amplifiers.
IEEE J. Solid State Circuits
34 (5) (1999)
Osamu Takahashi
,
Joel Silberman
,
Sang H. Dhong
,
H. Peter Hofstee
,
Naoaki Aoki
A 690 ps read-access latency register file for a GHz integer microprocessor.
ICCD
(1998)
Joel Silberman
,
Naoaki Aoki
,
David Boerstler
,
Jeffrey L. Burns
,
Sang H. Dhong
,
Axel Essbaum
,
Uttam Ghoshal
,
David F. Heidel
,
H. Peter Hofstee
,
Kyung T. Lee
,
David Meltzer
,
Hung C. Ngo
,
Kevin J. Nowka
,
Stephen D. Posluszny
,
Osamu Takahashi
,
Ivan Vo
,
Brian A. Zoric
A 1.0-GHz single-issue 64-bit powerPC integer processor.
IEEE J. Solid State Circuits
33 (11) (1998)
Stephen D. Posluszny
,
Naoaki Aoki
,
David Boerstler
,
Jeffrey L. Burns
,
Sang H. Dhong
,
Uttam Ghoshal
,
H. Peter Hofstee
,
David P. LaPotin
,
Kyung T. Lee
,
David Meltzer
,
Hung C. Ngo
,
Kevin J. Nowka
,
Joel Silberman
,
Osamu Takahashi
,
Ivan Vo
Design methodology for a 1.0 GHz microprocessor.
ICCD
(1998)