Jeffrey L. Burns

Publication Activity (10 Years)

Years Active: 1986-2017
Publications (10 Years): 1

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Publications

Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash
Panel discussions: "Cool chips for the next decade". COOL Chips (2017)
Jeffrey L. Burns
Technology trends and implications on SoC design. SoCC (2011)
Alan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Burns, Richard B. Brown
Resonant clocking using distributed parasitic capacitance. IEEE J. Solid State Circuits 39 (9) (2004)
Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown
Analysis and Optimization of Enhanced MTCMOS Scheme. VLSI Design (2004)
Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown
Efficient techniques for gate leakage estimation. ISLPED (2003)
Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. ICCAD (2003)
Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
Leakage and leakage sensitivity computation for combinational circuits. ISLPED (2003)
Juan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman
A semi-custom voltage-island technique and its application to high-speed serial links. ISLPED (2003)
Vikas Chandra, Gary D. Carpenter, Jeffrey L. Burns
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. ICCD (2003)
Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown
Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies. ESSCIRC (2003)
Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns
A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. IEEE J. Solid State Circuits 37 (11) (2002)
Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns
Performance Driven Synthesis for Pass-Transistor Logic. VLSI Design (1999)
H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi
Designing for a gigahertz [guTS integer processor]. IEEE Micro 18 (3) (1998)
Rajat Chaudhry, Tai-Hung Liu, Adnan Aziz, Jeffrey L. Burns
Area-oriented synthesis for pass-transistor logic. ICCD (1998)
Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric
A 1.0-GHz single-issue 64-bit powerPC integer processor. IEEE J. Solid State Circuits 33 (11) (1998)
Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo
Design methodology for a 1.0 GHz microprocessor. ICCD (1998)
Jeffrey L. Burns, Jack A. Feldman
C5M-a control-logic layout synthesis system for high-performance microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (1) (1998)
Jeffrey L. Burns, Jack A. Feldman
C5M - a control logic layout synthesis system for high-performance microprocessors. ISPD (1997)
Venkat K. R. Chiluvuri, Israel Koren, Jeffrey L. Burns
The Effect of Wire Length Minimization on Yield. DFT (1994)
Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma
Techniques for multilayer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (6) (1988)
Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli
Chameleon: a new multi-layer channel router. DAC (1986)