Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs.
Vikas ChandraGary D. CarpenterJeffrey L. BurnsPublished in: ICCD (2003)
Keyphrases
- low power
- power consumption
- synchronous communication
- nm technology
- asynchronous communication
- low cost
- high speed
- single chip
- high power
- power saving
- hardware and software
- power reduction
- low power consumption
- power dissipation
- wireless transmission
- digital signal processing
- vlsi architecture
- logic circuits
- design space exploration
- image processing
- real time
- gate array
- cmos technology
- design space
- low complexity