Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies.
Rahul M. RaoJeffrey L. BurnsRichard B. BrownPublished in: ESSCIRC (2003)
Keyphrases
- cmos technology
- low voltage
- circuit design
- high speed
- low power
- leakage current
- analog vlsi
- vlsi circuits
- nm technology
- metal oxide semiconductor
- power consumption
- delay insensitive
- long term
- parallel processing
- current status
- power dissipation
- field effect transistors
- chip design
- real time
- advanced technologies
- multiple input
- objective function
- silicon on insulator
- future trends
- paradigm shift
- emerging technologies
- future development
- web technologies
- low cost