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A 690 ps read-access latency register file for a GHz integer microprocessor.
Osamu Takahashi
Joel Silberman
Sang H. Dhong
H. Peter Hofstee
Naoaki Aoki
Published in:
ICCD (1998)
Keyphrases
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access latency
prefetching
high speed
floating point
scheduling algorithm
cache hit ratio
response time
data broadcast
file system
multi channel
web documents
access patterns
mobile clients
image quality
operating system
power consumption