256 Mb DRAM with ×32 both-ends DQ.
Yohji WatanabeRing WongToshiaki KirihataDaisuke KatoJohn K. DeBrosseTakahiko RaraMunehiro YoshidaRideo MukaiKhandker N. QuaderTakeshi NagaiPeter PoechmuellerPeter PfefferlMatthew R. WordemanShuso FujiiPublished in: IEEE J. Solid State Circuits (1996)