Peter Poechmueller

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 3

Top Topics

Immune Genetic Algorithm

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Heguo Yin, Peter Poechmueller
Semiconductor Application Fail Root Causes And Secure Test Remedy. ETS (2024)
Ranran Zhou, Haozhe Wang, Peng Wang, Peter Poechmueller, Yong Wang
A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads. IEEE Trans. Very Large Scale Integr. Syst. 31 (12) (2023)
Ranran Zhou, Peter Poechmueller, Yong Wang
An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman
, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. IEEE J. Solid State Circuits 34 (11) (1999)
Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii
256 Mb DRAM with ×32 both-ends DQ. IEEE J. Solid State Circuits 31 (4) (1996)
Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao
Fault-tolerant designs for 256 Mb DRAM. IEEE J. Solid State Circuits 31 (4) (1996)
Peter Poechmueller, Manfred Glesner, Fang Longsen
High-level synthesis transformations for programmable architectures. EURO-DAC (1993)
Peter Poechmueller, Hans-Jürgen Herpel, Manfred Glesner, Fang Longsen
High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment. FPL (1992)
Norbert Wehn, Hans-Jürgen Herpel, Thomas Hollstein, Peter Poechmueller, Manfred Glesner
High-level synthesis in a rapid-prototype environment for mechatronic systems. EURO-DAC (1992)
Peter Poechmueller, Michael Held, Norbert Wehn, Manfred Glesner
HADES-high-level architecture development and exploration system. Great Lakes Symposium on VLSI (1991)
Peter Poechmueller, Manfred Glesner
A New Approach for Designing Fault-Tolerant Array Processors. Fault-Tolerant Computing Systems (1991)
Peter Poechmueller, G. K. Sharma, Manfred Glesner
A CAD tool for designing large, fault-tolerant VLSI arrays. Great Lakes Symposium on VLSI (1991)
Peter Poechmueller, Manfred Glesner
An approach for multilevel logic cell optimization in module generators. Great Lakes Symposium on VLSI (1991)