Oliver Weinfurtner

Publication Activity (10 Years)

Years Active: 1998-2000
Publications (10 Years): 0

Publications

Oliver Weinfurtner, Daniel W. Storaska, Louis Hsu
Advanced controlling scheme for a DRAM voltage generator system. IEEE J. Solid State Circuits 35 (4) (2000)
Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman
cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. IEEE J. Solid State Circuits 35 (5) (2000)
Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman
, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. IEEE J. Solid State Circuits 34 (11) (1999)
Toshiaki Kirihata, Martin Gall, Kohji Hosokawa, Jean-Marc Dortu, Hing Wong, Peter Pfefferl, Brian L. Ji, Oliver Weinfurtner, John K. DeBrosse, Hartmud Terletzki, Manfred Selz, Wayne Ellis, Matthew R. Wordeman, Oliver Kiehl
, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. IEEE J. Solid State Circuits 33 (11) (1998)