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cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.

Heinz HoenigschmidAlexander FreyJohn K. DeBrosseToshiaki KirihataGerhard MuellerDaniel W. StoraskaGabriel DanielGerd FrankowskyKevin P. GuayDavid R. HansonLouis Lu-Chen HsuBrian JiDmitry G. NetisSteve PanaroniCarl RadensArmin M. ReithHartmud TerletzkiOliver WeinfurtnerJohann AlsmeierWerner WeberMatthew R. Wordeman
Published in: IEEE J. Solid State Circuits (2000)
Keyphrases
  • management system
  • software architecture
  • real time
  • mobile devices
  • high speed
  • ubiquitous environment
  • storage devices
  • neural network
  • wireless sensor networks
  • penalty term
  • programmable logic