Heinz Hoenigschmid

Publication Activity (10 Years)

Years Active: 1997-2010
Publications (10 Years): 0

Publications

Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein
A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques. IEEE J. Solid State Circuits 45 (1) (2010)
Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein
75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques. ISSCC (2009)
Stefan Dietrich, Michael Angerbauer, Milena Ivanov, Dietmar Gogl, Heinz Hoenigschmid, Michael Kund, Corvin Liaw, Michael Markert, Ralf Symanczyk, Laith Altimime, Serge Bournat, Gerhard Müller
A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control. IEEE J. Solid State Circuits 42 (4) (2007)
Heinz Hoenigschmid, P. Beer, Alexander Bette, R. Dittrich, R. Gardic, Dietmar Gogl, Stefan Lammers, J. Schmid, Laith Altimime, Serge Bournat, Gerhard Müller
Signal-Margin-Screening for Multi-Mb MRAM. ISSCC (2006)
Dietmar Gogl, Christian Arndt, John C. Barwin, Alexander Bette, John K. DeBrosse, Earl T. Gow, Heinz Hoenigschmid, Stefan Lammers, Mark C. Lamorey, Yu Lu, Tom Maffitt, Kim Maloney, Werner Obermaier, Andre Sturm, Hans Viehmann, Dennis R. Willmott, Mark A. Wood, William J. Gallagher, Gerhard Mueller, Arkalgud R. Sitaram
A 16-Mb MRAM featuring bootstrapped write drivers. IEEE J. Solid State Circuits 40 (4) (2005)
John K. DeBrosse, Dietmar Gogl, Alexander Bette, Heinz Hoenigschmid, Raphael Robertazzi, Christian Arndt, Daniel Braun, D. Casarotto, Robert Havreluk, Stefan Lammers, Werner Obermaier, William R. Reohr, Hans Viehmann, William J. Gallagher, Gerhard Müller
A high-speed 128-kb MRAM core for future universal memory applications. IEEE J. Solid State Circuits 39 (4) (2004)
Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman
cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. IEEE J. Solid State Circuits 35 (5) (2000)
Georg Braun, Heinz Hoenigschmid, Tobias Schlager, Werner Weber
ferroelectric RAM cell with depletion device (DeFeRAM). IEEE J. Solid State Circuits 35 (5) (2000)
Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman
, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. IEEE J. Solid State Circuits 34 (11) (1999)
Heinz Hoenigschmid, Mitiko Miura-Manausch, Odin Prigge, Alexander Rahm, Dominique Savignac
Optimization of advanced MOS technologies for narrow distribution of circuit performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (2) (1997)