Wolfgang Spirkl

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 5

Top Topics

Multi Dimensional

Cost Effectiveness

Top Venues

IEEE J. Solid State Circuits

Publications

Timothy M. Hollis, Ronny Schneider, Martin Brox, Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon Garrido, David Ovard, Karl Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez Gonzalez, Cristian Chetreanu, Andrea Sorrentino, Jörg Weller, Peter Mayer, Michael Richter, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling. IEEE J. Solid State Circuits 57 (1) (2022)
Timothy M. Hollis, Ronny Schneider, Martin Brox, Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon Garrido, David Ovard, Karl Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez Gonzalez, Martin Broschwitz, Cristian Chetreanu, Andrea Sorrentino, Jörg Weller, Peter Mayer, Michael Richter, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong
25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling. ISSCC (2021)
Martin Brox, Mani Balakrishnan, Martin Broschwitz, Cristian Chetreanu, Stefan Dietrich, Fabien Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, Milena Ivanov, Maksim Kuzmenka, Chris Mohr, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, Peter Pfefferl, Manfred Plan, Jens Polney, Stephan Rau, Michael Richter, Ronny Schneider, Ralf Oliver Seitter, Wolfgang Spirkl, Marc Walter, Jörg Weller, Filippo Vitale
An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications. IEEE J. Solid State Circuits 53 (1) (2018)
Seung-Jun Bae, Wolfgang Spirkl, Leland Chang
Session 12 overview: DRAM: Memory subcommittee. ISSCC (2018)
Martin Brox, Mani Balakrishnan, Martin Broschwitz, Cristian Chetreanu, Stefan Dietrich, Fabien Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, Milena Ivanov, Maksim Kuzmenka, Chris Mohr, Francisco Emiliano Munoz, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, Peter Pfefferl, Manfred Plan, Jens Polney, Stefan Rau, Michael Richter, Ronny Schneider, Ralf Oliver Seitter, Wolfgang Spirkl, Marc Walter, Jörg Weller, Filippo Vitale
23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications. ISSCC (2017)
Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein
A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques. IEEE J. Solid State Circuits 45 (1) (2010)
Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein
75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques. ISSCC (2009)
Thomas Nirmaier, Jose Torres Zaguirre, Eric Liau, Wolfgang Spirkl, Armin Rettenberger, Doris Schmitt-Landsiedel
Efficient High-Speed Interface Verification and Fault Analysis. ITC (2008)
Martin Brox, H. Fibranz, Maksim Kuzmenka, F. Lu, S. Mann, M. Markert, U. Möller, Manfred Plan, Kai Schiller, P. Schmölz, P. Schrögmeier, A. Täuber, Bradley Weber, Peter Mayer, Wolfgang Spirkl, Holger Steffens, Jörg Weller
A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniques. ISSCC (2006)
Thomas Nirmaier, Wolfgang Spirkl, Eric Liau Chee Hong
Fully automated semiconductor operating condition testing. ITC (2006)