, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.
Toshiaki KirihataMartin GallKohji HosokawaJean-Marc DortuHing WongPeter PfefferlBrian L. JiOliver WeinfurtnerJohn K. DeBrosseHartmud TerletzkiManfred SelzWayne EllisMatthew R. WordemanOliver KiehlPublished in: IEEE J. Solid State Circuits (1998)