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Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator.

Naoya AzumaShunsuke ShimazakiNoriyuki MiuraMakoto NagataTomomitsu KitamuraSatoru TakahashiMotoki MurakamiKazuaki HoriAtsushi NakamuraKenta TsukamotoMizuki IwanamiEiji HankuiSho MurogaYasushi EndoSatoshi TanakaMasahiro Yamaguchi
Published in: IEICE Trans. Electron. (2014)
Keyphrases
  • low cost
  • high speed
  • noisy data
  • missing data
  • circuit design
  • noise level
  • analog vlsi
  • signal to noise ratio
  • random noise
  • received signal
  • cmos image sensor