Login / Signup
Sho Muroga
ORCID
Publication Activity (10 Years)
Years Active: 2013-2020
Publications (10 Years): 3
Top Topics
Circuit Design
Grain Size
Thin Film
Noise Suppression
Top Venues
EMC Compo
IEICE Electron. Express
IEICE Trans. Commun.
IEICE Trans. Electron.
</>
Publications
</>
Sho Muroga
,
Motoshi Tanaka
,
Takefumi Yoshikawa
,
Yasushi Endo
Effect of Complex Permeability on Circuit Parameters of CPW with Magnetic Noise Suppression Sheet.
IEICE Trans. Commun.
(9) (2020)
Takefumi Yoshikawa
,
Tatsuya Iwata
,
Junji Shibazaki
,
Sho Muroga
,
Hiroaki Ikeda
A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus.
IEICE Electron. Express
17 (10) (2020)
Satoshi Tanaka
,
Peng Fan
,
Jingyan Ma
,
Hanae Aoki
,
Masahiro Yamaguchi
,
Makoto Nagata
,
Sho Muroga
Analysis of on-chip digital noise coupling path for wireless communication IC test chip.
EMC Compo
(2015)
Naoya Azuma
,
Shunsuke Shimazaki
,
Noriyuki Miura
,
Makoto Nagata
,
Tomomitsu Kitamura
,
Satoru Takahashi
,
Motoki Murakami
,
Kazuaki Hori
,
Atsushi Nakamura
,
Kenta Tsukamoto
,
Mizuki Iwanami
,
Eiji Hankui
,
Sho Muroga
,
Yasushi Endo
,
Satoshi Tanaka
,
Masahiro Yamaguchi
Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator.
IEICE Trans. Electron.
(6) (2014)
Naoya Azuma
,
Shunsuke Shimazaki
,
Noriyuki Miura
,
Makoto Nagata
,
Tomomitsu Kitamura
,
Satoru Takahashi
,
Motoki Murakami
,
Kazuaki Hori
,
Atsushi Nakamura
,
Kenta Tsukamoto
,
Mizuki Iwanami
,
Eiji Hankui
,
Sho Muroga
,
Yasushi Endo
,
Satoshi Tanaka
,
Masahiro Yamaguchi
Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator.
EMC Compo
(2013)
Sho Muroga
,
Y. Shimada
,
Yasushi Endo
,
Satoshi Tanaka
,
Masahiro Yamaguchi
,
Naoya Azuma
,
Makoto Nagata
,
Motoki Murakami
,
Kazuaki Hori
,
Satoru Takahashi
In-band spurious attenuation in LTE-class RFIC chip using a soft magnetic thin film.
EMC Compo
(2013)