/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM.
Noriyuki MiuraKazutaka KasugaMitsuko SaitoTadahiro KurodaPublished in: ISSCC (2010)
Keyphrases
- cmos technology
- low voltage
- parallel processing
- dynamic random access memory
- user interface
- inductive learning
- low power
- main memory
- silicon on insulator
- real time
- graphics hardware
- machine learning
- nm technology
- metal oxide semiconductor
- parallel implementation
- high speed
- image sensor
- high density
- power dissipation
- user friendly
- power consumption
- embedded dram
- low cost
- inductive inference
- design considerations
- knowledge representation