Jun Shiomi

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 48

Top Topics

Lognormal Distribution

Evaluation Metrics

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEICE Trans. Electron.

Publications

Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi
Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits. ASPDAC (2024)
Itsuki Takada, Daiki Nitto, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi, Ryoichi Shinkuma
Edge-Oriented Point Cloud Compression by Moving Object Detection for Realtime Smart Monitoring. CCNC (2024)
Dehua Liang, Jun Shiomi, Noriyuki Miura, Hiromitsu Awano
StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification. IEEE Open J. Circuits Syst. 5 (2024)
Kotaro Naruse, Takayuki Ueda, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura
A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication. ISSCC (2023)
Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi
Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations. IEICE Trans. Electron. 106 (10) (2023)
Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata
A Triturated Sensing System. ISSCC (2023)
Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Dehua Liang, Hiromitsu Awano, Noriyuki Miura, Jun Shiomi
DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits. ASP-DAC (2023)
Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi
Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations. COOL CHIPS (2022)
Dehua Liang, Jun Shiomi, Noriyuki Miura, Hiromitsu Awano
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification. ASP-DAC (2022)
Dehua Liang, Jun Shiomi, Noriyuki Miura, Masanori Hashimoto, Hiromitsu Awano
A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. IEICE Trans. Inf. Syst. (7) (2022)
Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region. LASCAS (2022)
Kuon Akiyama, Ryoichi Shinkuma, Jun Shiomi
Real-time adaptive data filtering with multiple sensors for indoor monitoring. NOMS (2022)
Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. SOCC (2022)
Hongjie Xu, Jun Shiomi, Hidetoshi Onodera
Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2021)
Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera
A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation. IEICE Trans. Electron. (10) (2021)
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2021)
Hongjie Xu, Jun Shiomi, Hidetoshi Onodera
MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching. IEEE Open J. Circuits Syst. 2 (2021)
Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2021)
Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. ISQED (2021)
Jun Shiomi, Shuya Kotsugi, Boyu Dong, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics. DAC (2021)
Naoki Hattori, Jun Shiomi, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2021)
Khyati Kiyawat, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. ISVLSI (2020)
Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region. SoCC (2020)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. ICRC (2020)
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. ISVLSI (2020)
Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera
A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias. APCCAS (2020)
Hongjie Xu, Jun Shiomi, Hidetoshi Onodera
On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation. ACM Great Lakes Symposium on VLSI (2020)
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. ASP-DAC (2019)
Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi
An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. PHOTONICS@SC (2019)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. Integr. 65 (2019)
Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
A Design Method of a Cell-Based Amplifier for Body Bias Generation. IEICE Trans. Electron. (7) (2019)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. ICRC (2018)
Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. PATMOS (2018)
Jun Shiomi, Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
Minimum Energy Point Tracking with All-Digital On-Chip Sensors. J. Low Power Electron. 14 (2) (2018)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera
Pin accessibility evaluating model for improving routability of VLSI designs. SoCC (2017)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. PATMOS (2016)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Variability- and correlation-aware logical effort for near-threshold circuit design. ISQED (2016)
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. ASP-DAC (2016)
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Microarchitectural-level statistical timing models for near-threshold circuit design. ASP-DAC (2015)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. IEEE J. Solid State Circuits 50 (11) (2015)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
An energy-efficient on-chip memory structure for variability-aware near-threshold operation. ISQED (2015)
Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring. A-SSCC (2014)